Field of the Disclosure
This application relates generally to processing systems and, more particularly, to a memory physical layer interface in a processing system.
Description of the Related Art
Processing systems such as systems-on-a-chip (SOCs) use memory to store data or instructions for later use. For example, an SOC may include processing units such as central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs) can read instructions or data from memory, perform operations using the instructions or data, and then write the results back into the memory. Processing systems may include a memory physical layer interface for controlling access to a memory module such as dynamic random access memory (DRAM) that can be used to store information so that the stored information can be accessed by the processing units during operation of the processing system. The memory physical layer interface in a processing system is conventionally referred to as a “memory PHY.” A memory controller is typically used to control operation of the memory PHY.
The memory PHY typically is trained using sequences exchanged over an interface between the memory PHY and the DRAM before data can be accurately read from the DRAM or written to the DRAM. The interface training procedure may include a global interface initialization mechanism to perform a relatively coarse-grained synchronization of command issuing and data sample timing at the interface endpoints for reading and writing. The training sequence for the global synchronization may be, for example, constructed with a continuous stream of DRAM commands, punctuated in a periodic fashion with a command gap that may be referred to as a “bubble.” This sequence creates a series of time/event markers inside the continuous stream that can be used to frame or synchronize coarse/global interface timing. A finer-grained per-signal training procedure may then be used to find the optimal timing and voltage offset for sampling the data signal. The training sequence for the per-signal training procedure may include a random mix of “1s” and “0s” that are read from and/or written to the DRAM. Signals returned from the DRAM in response to the training sequence are used to determine the contour of a “data eye,” which is a plot that shows the rising edge, the falling edge, and the high/low voltages that represent a value of a data signal as a function of time and voltage.
Conventional training procedures are initiated by BIOS code running on a processor in the processing system. However, the BIOS is typically logically or physically remote from the memory PHY. For example, the BIOS and the memory PHY may be separated by a data pipelines, memory caches, and buffers. These intervening interfaces and subsystem blocks may distort or alter training control and data sequences transmitted from the BIOS, e.g., additional bubbles may be introduced into the training sequence making it more difficult to find efficient training algorithms. Consequently, the BIOS typically incorporates complex training sequence seeding and data post-processing schemes into the training code. Both approaches have significant drawbacks. For example, the additional time required to move, mine, and operate on the data during post-processing increases the overall time required to perform training If the total training time budget is fixed, then the additional time spent in post-processing means that time must be saved elsewhere to keep the overall training time within budget. Time may be saved by running shorter patterns, which may result in a larger training error. For another example, training sequence seeding is used to start the training from a system state where the pipeline issues described above that could prevent the algorithm from converging are avoided, but finding the appropriate seed values to correctly define the initial system state requires extensive system and platform characterization. The seed values may include information that characterizes the data pipeline, the memory PHY, or other logical or physical entities along the path from the BIOS, through the memory PHY to the DRAM, and back to the BIOS. Each of the seed values must be characterized in the lab for each processing system or implementation of DRAM. Consequently, the quantity and variety of seed information that must be generated is expanding rapidly as the number and diversity of processing systems and associated memory devices increases, which may increase the BIOS code size and make the BIOS more difficult to maintain.